Espressif Systems /ESP32 /I2C0 /SR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as SR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (ACK_REC)ACK_REC 0 (SLAVE_RW)SLAVE_RW 0 (TIME_OUT)TIME_OUT 0 (ARB_LOST)ARB_LOST 0 (BUS_BUSY)BUS_BUSY 0 (SLAVE_ADDRESSED)SLAVE_ADDRESSED 0 (BYTE_TRANS)BYTE_TRANS 0RXFIFO_CNT0TXFIFO_CNT0SCL_MAIN_STATE_LAST 0SCL_STATE_LAST

Fields

ACK_REC

This register stores the value of ACK bit.

SLAVE_RW

when in slave mode 1: master read slave 0: master write slave.

TIME_OUT

when I2C takes more than time_out_reg clocks to receive a data then this register changes to high level.

ARB_LOST

when I2C lost control of SDA line this register changes to high level.

BUS_BUSY

1:I2C bus is busy transferring data. 0:I2C bus is in idle state.

SLAVE_ADDRESSED

when configured as i2c slave and the address send by master is equal to slave’s address then this bit will be high level.

BYTE_TRANS

This register changes to high level when one byte is transferred.

RXFIFO_CNT

This register represent the amount of data need to send.

TXFIFO_CNT

This register stores the amount of received data in ram.

SCL_MAIN_STATE_LAST

This register stores the value of state machine for i2c module. 3’h0: SCL_MAIN_IDLE 3’h1: SCL_ADDRESS_SHIFT 3’h2: SCL_ACK_ADDRESS 3’h3: SCL_RX_DATA 3’h4 SCL_TX_DATA 3’h5:SCL_SEND_ACK 3’h6:SCL_WAIT_ACK

SCL_STATE_LAST

This register stores the value of state machine to produce SCL. 3’h0: SCL_IDLE 3’h1:SCL_START 3’h2:SCL_LOW_EDGE 3’h3: SCL_LOW 3’h4:SCL_HIGH_EDGE 3’h5:SCL_HIGH 3’h6:SCL_STOP

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